The invention relates to a method of manufacturing a semiconductor device comprising a semiconductor body one surface of which is provided with a pair of transistors in the form of an n-channel MOST in a first active region and a p-channel MOST in a second active region, in combination with a non-volatile memory cell in the form of a MOST having a floating gate in a third active region. Customarily, the MOST having a floating gate is an n-channel transistor, but it may of course also be a transistor with a p-channel. Such a method is disclosed, inter alia, in U.S. Pat. No. 5,395,778, in the name of the current applicant. In said patent, a description is given of a method which can very advantageously be used in the manufacture of an integrated circuit having an embedded, non-volatile memory, in which method a standard CMOS process for the digital signal processing logic is used to provide such a circuit "on chip" with a memory by adding as few extra steps as possible. To optimize the properties of the memory, for example as regards the write efficiency, without adversely affecting the properties of the logic, in a first series of steps the major part of the memory transistor having the floating gate and the source and drain zones are formed, while the region in which the logic is provided at a later stage remains covered by a layer of polycrystalline (poly) or amorphous silicon from which the floating gate is made.
The various embodiments of this known process are such that transistors of the n-channel type and of the p-channel type are formed in the logic, which transistors both comprise an n-type doped poly gate electrode. However, it is often desirable, for example in connection with the threshold voltage of the transistor, that the n-channel transistor has an n-type gate and the p-channel transistor has a p-type gate. When an n-type gate is employed in the p-channel transistor, a buried channel is often formed, as a result of which an additional voltage is necessary to bring the transistor into the off-state. This may be undesirable, in particular, when the channel length is very small, for example 0.5 .mu.m or less, in which case also a lower supply voltage is used.